Name: (DF5A) Democratizing Chiplets - In the Physical AI Era
Uploaded: 2026-06-23T19:30:16.108Z
Duration: 21 min 8 s
Description: (DF5A) Democratizing Chiplets - In the Physical AI Era

Transcript for "(DF5A) Democratizing Chiplets - In the Physical AI Era": Welcome to the presentation, democratizing chiplets in the physical AI era. My name is Mick Posner, and I'm the group director of chiplets solutions at Cadence. Today, we're gonna cover a number of topics, chiplet evolution, current state and the future desired state, chiplet technology fundamentals for the future, addressing the complexity of chiplet based designs, the need for standardization, and we'll finish with the value of collaboration. Before we look forward, let's look backwards. Design disaggregation and the rise of multi die. In 2025, the chiplet narrative was dominated by disaggregation for massive data centers. We talked about the trends driving semiconductor TAM growth, including the need for disaggregation, the explosion of compute demands driven by AI, and the need to move away from a monolithic SoC tube chiplet based architectures given cost and complexities of process technology scaling on monolithic SoCs. While multi di helped address scalability and performance, much of the development was proprietary. 2026 marks a critical turning point. The story is changing from closed environments to a true interoperable ecosystem. We're entering an era where the focus is to enable chiplets you can buy off the shelf, where components from different vendors can be plugged and played, connected, leveraging the power of package level scaling. So what is driving the need for advances in system design? There are really three major phases in time and three fundamental layers of AI impact to silicon and system design complexity. We've all witnessed the infrastructure AI build out, data centers with massive CPU GPU infrastructures. What is fascinating is to be part of and witness the advent of the second horizon, which we call physical AI, AI driven by autonomy and senses. The world of autonomous cars, drones, robotics, domain specific silicon will be transformational. The third phase of AI will be in the realms of life sciences from DNA to rapid molecular design to deep understanding of large life science systems that no longer rely on prediction and iterative estimations. Let's focus on physical AI and its enablement. The next step in the AI evolution is what we call physical AI, autonomous vehicles, drones, robotics, aerospace, and defense. These are intelligent systems that need to interact with the real world. They sense. They reason. They act. All these physical AI applications have similar characteristics. They all need CPU processing. They all need AI acceleration, and they all need interfaces to memory and system components. This makes physical AI applications perfect to be disaggregated into chiplet based architectures. As a reminder, chiplet architectures deliver cost efficiency, customization, and configurability. Cost efficiency, you can focus on your unique value add utilizing off the shelf chiplets for the remaining function. Customization, modular design, build small to large solutions with the same set of chiplet building blocks. And configurability, manage your product portfolio through reuse and chiplets diversification. Only upgrade the chiplets that need upgrading. And the fourth c of chiplets is you require a partner for success, and this is where the cadence and cadence ecosystem comes in. We deliver EDA tools, IP, chiplets, and design services to make you successful. With those trends in mind, it's important to look at the fundamentals of chiplets and how these are evolving in the era of physical AI. There are still many challenges to broad industry adoption of chiplets. Three of the main challenges are complexity, the ability to plug and play chiplets with each other, and the supply chain and ecosystem. If we look at our current state, specific expertise is required for chiplet design. There are still many proprietary architectures and interfaces, and the ecosystem is fragmented. Where do we need to be? Well, we need enhanced EDA and triplet reference platforms. This will help accelerate the design of triplet based systems. To enable plug and play, we need open triplet standardization. And then to address the fragmentation of the ecosystem, we need new cohesive ecosystems enabling a real chiplet marketplace. Realizing the promise of an interoperable chiplet ecosystem requires industry wide collaboration. So what can be done to address complexity? Availability to reference platforms accelerate development and lowers risk. Having a starting point for chiplet based design is critical. Cadence offers platforms for physical AI and common data center and infrastructure chiplets, such as IO and memory extenders. Having available and ready to utilize platforms reduces the expertise required to develop and significantly accelerates the availability of deliverables. Platforms which support configuration and customization allows the design to be quickly aligned to specific customer requirements while lowering risk from reuse. In addition to the platforms, Cadence has invested in EDA technology and flows, which enables these platforms to be rapidly configured and customized and then automatically generated through a crew wrecked by construction flow. The automated flow to simulation and emulation means designers can start their verification and software development early. While we are talking about simulation and emulation, Cadence has also prebuilt a complete Arm Neoverse v three compute subsystem, complementing the Arm system with Cadence IP for PCIe, CXL, memory, and UCIE. The simulation and emulation environments ensure that Cadence IP is interoperability tested against the ARM platform. This platform enables early software development and with the UCIE connection enables chiplet to chiplet verification to start. Now that we've shown how complexity can be addressed with reference platforms, let's talk about the importance of universal Chiplex standardization. Standardization ensures Chiplex will work together seamlessly. The benefits of standardization are clear. Firstly, interoperability. This will enable the integration of chiplets from different vendors. It will lead to cost efficiency. Interoperability will enable the reuse of design and processes. Standardization means faster time to market, leverage standardized chiplet components, and standardization will jump start the chiplet marketplace. Recently, ARM contributed their chiplet system architecture to OCP, and OCP created the foundation chiplet system architecture, FCSA. This is by far the most mature vendor neutral, architecture agnostic, and it acts as the specification which will be a common baseline for interoperable chiplets. You can also help drive this standardization by getting involved in the OCP open chiplet economy. To accelerate the adoption of standards based chiplets, Cadence has created the chiplet framework. The chiplet framework enables chiplets of all applications. It is standards based for interoperability, supporting arms, triplet system architecture, and OCP foundation triplet system architecture. It utilizes UCIE for die to die connectivity, also a standard interface. The chiplet framework is a comprehensive generated hardware and software framework. It manages system control, which includes delivery of reference software. It includes a secure route of trust for boot, attestation, and security life cycle management. It offers subsystems for debug, network on chip, and UCIE die to die connectivity. And for autonomous and other physical AI, it has an optional safety management system. Finally, let's talk about what's needed to jump start the ecosystem and chiplet marketplace. The key to enabling a chiplet marketplace is moving from proprietary solutions to an open ecosystem. An open ecosystem is needed for the chiplets of the future, and this requires collaboration. Collaboration means you're accessing diverse perspectives. You're leveraging expertise. It can help foster innovation, and it opens new doors for opportunities. And it solves challenges faster with collective effort. This is where we need to stop focusing on disaggregation, and we need to move to looking at aggregation of chiplets across many vendors. Stop focusing on pure infrastructure AI and expand it to infrastructure and physical AI, and stop looking at proprietary solutions that leave a very fragmented market and focus on standards based, configurable, and off the shelf. Ecosystems accelerate triplet time to market. One such example is the Cadence partner ecosystem focused on accelerating triplet time to market. This is an ecosystem of partners delivering end to end solutions for physical AI and infrastructure AI chiplets. So in conclusion, what we've discussed today is making chiplets for everyone a reality. Leverage platforms to accelerate development and lower risk. Utilize the cadence reference platforms to accelerate your physical AI and infrastructure chiplets. Get involved, help drive OCP F CSA standardization and the evolution of chiplet based systems and collaborate to foster ecosystems and jump start the chiplet marketplace. For more information on the Cadence Chiplet solutions, please visit www.cadence/gochiplets. There, you'll find more information on our physical AI chiplet platform targeted at automotive, drones, robotics, aerospace, and defense. You'll find more information on our infrastructure, chiplets targeting data center and infrastructure applications. You'll also find more information on the Cadence Chiplets framework, which is a silicon proven framework enabling domain specific and interoperable chiplets. Thank you for your time today, and I hope you found this presentation valuable and interesting.